PURPOSE:To improve the degree of freedoms of wirings by forming holes at positions opposed to electric connections of an insulating film formed on a pattern made of a polycrystalline silicon layer and a cutout of the silicon layer, further forming a pattern of a metal wiring layer and then etching the silicon layer. CONSTITUTION:A polycrystalline silicon is coated on a wiring region, and a pattern 4 of lattice shape is formed. Then, a CVD-SiO2 film 5 is formed on the pattern 4, holes 6, 6 are formed at the positions of electric connections, and holes 7, 7... are formed at the positions opposed to the cut positions of the pattern 4. Subsequently, aluminum is deposited on the film 5, and patterns 81, 82 are formed. Then, when a plasma etching of CF4 and O2 is performed, the pattern 4 is etched at the hole 7 which is not coated with the patterns 81, 82 of an aluminum wiring layer, partly cut, and the wiring patterns of aluminum wiring layers 81, 82 are formed. Thus, the polycrystalline silicon layer can be used for master-slice type programmable wirings, thereby reducing the size of a chip.