PURPOSE:To prevent the impairment of high-speed data transfer and to improve the throughput of a computer system by invalidating a low-speed bus request signal with a reserved signal input of a high-speed unit. CONSTITUTION:The high-speed bus request signals HRQ1...HRQY supplied from Y pieces of high-speed units are supplied directly to a bus request control circuit BRQC. While the AND operation is performed between an inhibit signal STOP and low-speed bus requests LRQ1...LRQX applied from X pieces of low- speed units through gates G1...GX. As a result, ARQ1...ARQX are supplied. The circuit BRQC delivers acceptance signals based on a high-speed bus request signal, the priority of the AND operation result and a reserved signal. Thus a low- speed request signal is invalidated for a fixed period of time. In other words, the impairment of the high-speed data transfer can be prevented by invalidating the low-speed bus request signal by the reserved signal supplied from the high-speed unit. This improves the throughput of a computer system.