PURPOSE:To reduce the number of transfer clocks down to half and at the same time to prevent the deterioration of the working margin of the titled semiconductor device, by connecting additional emitters to original emitters via resistances. CONSTITUTION:Additional emitters 60-64 are connected to emitters 21-25 through resistances 71-75 (resistance value RE') respectively. The transfer clocks are applied to these emitters and resistances every three units. Now conductance transistors CDT3 (23, 33, 43 and 53) are turned on by a transfer clock phi3. Under such conditions, the voltage of a high level is applied to a clock phi1. Then the emitter voltages of elements CDT4 (24, 34, 44 and 54) which are turned on next rise up. In this case, the positive holes are injected from the emitter 63. Therefore the conduction degree modulating area of the CDT3 is shifted and the conventional RC1 increases. As a result, the working margin can be improved as conventional.